Publicreport_wp4


Public Report Of The Project's Results: WP4 Back-side processing of the CMOS wafers

WP4: Back-side processing of the CMOS wafers

The processing steps which make up the BSI module are:

  1. Bonding of the CMOS device wafer to the carrier wafer.
  2. Grinding of the CMOS device wafer to a thickness < 30 μm.
  3. Wet etch.
  4. CMP (Chemical-Mechanical Polishing).
  5. Cavity etching.
  6. ARC deposition.
  7. Back-via etching.
  8. Back-pad deposition.

In the first step the carrier and device wafers are prepared followed by wafer-to-wafer oxide-oxide permanent bonding.

The SBRETFINAL wafers arrived at imec and after their bonding to the carrier wafers the quality of the bonding was verified using Scanning Acoustic Microscopy. Figure 1 shows the results of these checks for some of the wafers. Only one wafer showed air bubbles in the bottom-left corner, visible as white spots. Nevertheless the wafer went through the rest of the processing steps without being damaged.

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(c) (d)

Figure 1: SAM pictures of the wafers after bonding from lot P142296. (a) D02, (b) D03, (c) D05, (d) D06.

In the next step the wafers are thinned down. The following figure shows the thickness inspection at the end of step 4, using optical measurement tools. The mean thickness is very close to the 10.5 μm specification, with total thickness variation (TTV) around 3 μm.

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Figure 2: Thickness inspection: (a) D07, (b) D08.

After the wafers have been thinned, they are inspected for particles using an unpatterned surface inspection system. The figure below shows the results for two of the wafers.

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Figure 3: Particle inspection for two of the wafers.

The edge-trim region exclusion was too small and hence a lot of particles appear in the edges, increasing the particle counts. Excluding those numbers, the number of particles in the functional surface of the wafer is as expected.

The next step is to etch the CMOS silicon wafer from the silicon towards the metallization to create the cavity. After the cavity has been etched the wafer is inspected visually to check that the expected structures are visible. An example is shown in the next figure.



Figure 4: Cavity inspection after etching.

Once the cavity has been opened, an additional etching step is needed to reach the first metal in the metal stack to create the "back-via" before the Aluminium "back-pad" is created and the process is complete.

As there were no dummy structures in place to help the landing on the first metal layer, one wafer (a.k.a. "Send Ahead Wafer" or SAW) was used to do a cross-section and measure the layers with a scanning electron microscope. Figure 5 shows the cross-section in the pad area. Figure 6 shows a magnification of the area in the red circle.



Figure 5: Cross-section of one pad. The area in the red circle is shown in Figure 6.



Figure 6: Magnification of Figure 5.

The final SiN thickness of the two wafers is measured as shown in Figure 7 for D03 and Figure 9 for wafer D05. The different final ARC thickness is visible in the different color of the surface of the wafers.



Figure 7: SiN thickness of wafer D03 (units are in nm).



Figure 8: Picture of the D03 wafer at the end of the processing.



Figure 9: SiN thickness of wafer D05 (units are in nm).



Figure 10: Picture of the D05 wafer at the end of the processing.

Looking at the wafers under the microscope, one can see the final back-side pad deposited on top of the CMOS pad. This is more visible comparing Figure 4 with figure 11 and figure 12.



Figure 10: Microscope inspection of the D03 wafer at the end of the processing.



Figure 10: Microscope inspection of the D05 wafer at the end of the processing.